1. Field of the Invention
The present invention relates to a dielectric composite for use as an interpoly dielectric in non-volatile memory devices such as EPROM, EEPROM and flash EPROM devices.
2. Description of Related Art
Nonvolatile memory devices, such as EPROM, EEPROM and flash EPROM devices, are well known in the ad. In general, nonvolatile memory devices comprise a series of transistors which act as memory cells. Each transistor includes source and drain regions formed on the surface of a nor p- type semiconductor substrate, an insulating layer formed on the surface of the semiconductor substrate positioned between the source and drain regions, a floating gate positioned on the insulating layer for holding a charge, a layer of an insulating dielectric formed on the floating gate for insulating the floating gate, thereby enabling the floating gate to retain its charge and a control gate positioned on the insulating dielectric layer.
A bit of binary data is stored in the floating gate of each memory cell as either a high or low level charge, a high level charge corresponding to a first data value (e.g. 1), a low level charge corresponding to a second data value (e.g. 0). Since the value of the data stored in the floating gate is a function of the size of the charge stored in the floating gate, charge loss or gain by the floating gate can alter the value of the data stored in the memory cell. It is therefore essential to the functioning of a nonvolatile memory device that each floating gate be capable of long term charge retention.
The ability of a floating gate to retain a charge is primarily determined by the dielectric insulating material used to insulate the floating gate. In order to prevent charge loss, the dielectric must have a high break down voltage. For example, when a high potential is applied to the control gate during programming, the dielectric must have a sufficiently high breakdown voltage to block electrons from the floating gate to the control gate.
Once a charge is introduced into the floating gate, the dielectric must also be able to prevent charge leakage from the floating gate. Charge leakage generally occurs through "pinholes" and other defects in the dielectric layer. It is therefore very important for the insulating dielectric to have a high degree of structural integrity which is generally associated with a low concentration of pinholes.
Charges are transferred to a floating gate by a variety of methods, such as avalanche injection, channel injection and Fowler-Nordheim tunnelling. With all of these methods, the energy that must be expended to introduce a charge into the floating gate is a function of the capacitance between the floating gate and the control gate and hence is related to the thickness of the dielectric layer. In order to minimize the amount of energy needed to pass a charge into and out of the floating gate, as well as to minimize the amount of heat generated by the device, it is desirable to minimize the thickness of the insulating dielectric layer. However, as the thickness of the dielectric is reduced, charge leakage through pinholes and other defects in the dielectric generally increases.
Previously, a single layer of silicon dioxide was employed as the insulating dielectric layer. However, variations in the thickness of the single silicon dioxide layer, as well as defects (pinholes) in the single oxide layer limited the effectiveness of the single oxide layer to prevent charge leakage from the floating gate.
Oxide/nitride/oxide (ONO) dielectric composites have been developed that provide nonvolatile memory cells with enhanced charge retention over single oxide layers and thus have largely replaced single oxide layers in nonvolatile memory cells. In general, ONO refers to a composite dielectric which has a bottom silicon dioxide layer positioned adjacent to the floating gate, a middle layer composed of silicon nitride and a layer of silicon dioxide covering the silicon nitride layer. The control gate is positioned over the top oxide layer.
The middle nitride layer in the ONO dielectric composite is believed to provide enhanced charge retention by moderating thickness variation in the bottom oxide layer and local gate thinning at the gate corner. The nitride layer is also believed to plug defects in the bottom oxide layer, such as pinholes, thereby preventing charge leakage through the defects. The nitride layer has also been employed to trap charges leaked through the bottom oxide layer from the floating gate, thereby preventing charge leakage to the control gate. In view of these functions, the nitride layer has traditionally been the thickest or second thickest layer in prior art ONO composites.
For example, U.S. Pat. No. 4,630,086 teaches use of the nitride layer to trap charges that have leaked from the floating gate, thereby preventing charge leakage from the floating gate to the control gate. U.S. Pat. No. 4,630,086 also teaches use of the top oxide layer to prevent charges trapped in the nitride layer from leaking to the floating gate. Specifically, the '086 patent teaches an ONO composite having a 15-50 A bottom oxide layer, a 40 and 110 .ANG. middle nitride layer and a 20 .ANG. top oxide layer.
U.S. Pat. No. 5,104,819 teaches an alternative ONO composite dielectric in which the silicon nitride layer is between 50 and 150 .ANG. and the top oxide layer is relatively thick when compared to the underlying oxide and nitride layers. The '819 patent teaches that the bottom oxide layer is not critical to the functioning of the dielectric composite and may therefore be between 0 and 80 .ANG..